//***********************************************************************//
//*                                                                     *//
//*                      Copyright © 2022 AMI                           *//
//*                                                                     *//
//*        All rights reserved. Subject to AMI licensing agreement.     *//
//*                                                                     *//
//***********************************************************************//

/*
 * Smbus_mailbox.h
 *
 *      Author: presannar
 */

#ifndef PFR_SMBUS_MAILBOX_COMM_H_
#define PFR_SMBUS_MAILBOX_COMM_H_

typedef char byte;

typedef enum _PLATFORM_STATE_VALUE {
	CPLD_NIOS_II_PROCESSOR_WAITING_TO_START = 0X1,  // not set
	CPLD_NIOS_II_PROCESSOR_STARTED,                 // not set
	ENTER_T_MINUS_1,
	BMC_FLASH_AUTH                          = 0X6,
	PCH_FLASH_AUTH,
	LOCKDOWN_ON_AUTH_FAIL,
	ENTER_T0,
	T0_BMC_BOOTED,
	T0_ME_BOOTED,    // not set
	T0_ACM_BOOTED,
	T0_BIOS_BOOTED,
	T0_BOOT_COMPLETED,
	PCH_FW_UPDATE           = 0X10,
	BMC_FW_UPDATE,
	CPLD_FW_UPDATE,
	CPLD_FW_UPDATE_IN_RECOVERY_MODE,        // not used
	T_MINUS_1_FW_RECOVERY   = 0X40,
	T_MINUS_1_FORCED_ACTIVE_FW_RECOVERY,    // not used
	WDT_TIMEOUT_RECOVERY,
	CPLD_RECOVERY_IN_RECOVERY_MODE,         // not used
	LOCKDOWN_DUE_TO_PIT_l1,                 // not used
	PIT_L2_FW_SEALED,                       // not used
	LOCKDOWN_ON_PIT_L2_PCH_HASH_MISMATCH,   // not used
	LOCKDOWN_ON_PIT_L2_BMC_HASH_MISMATCH    // not used
} PLATFORM_STATE_VALUE;

typedef enum _LAST_RECOVERY_REASON_VALUE {
	PCH_ACTIVE_FAIL = 0x1,
	PCH_RECOVERY_FAIL,
	ME_LAUNCH_FAIL,         // not set
	ACM_LAUNCH_FAIL,        // not set
	IBB_LAUNCH_FAIL,        // not set
	OBB_LAUNCH_FAIL,        // not set
	BMC_ACTIVE_FAIL,
	BMC_RECOVERY_FAIL,
	BMC_LAUNCH_FAIL,        // not set
	CPLD_WDT_FAIL,          // not set
	FORCED_ACTIVE_RECOVERY  // not used
} LAST_RECOVERY_REASON_VALUE;

typedef enum _LAST_PANIC_REASON_VALUE {
	PCH_UPDATE_INTENT = 0x1,
	BMC_UPDATE_INTENT,
	BMC_RESET_DETECT,
	BMC_WDT_EXPIRE,
	ME_WDT_EXPIRE,          // not set
	ACM_WDT_EXPIRE,
	IBB_WDT_EXPIRE,         // not set
	OBB_WDT_EXPIRE,
	ACM_IBB_0BB_AUTH_FAIL

} LAST_PANIC_REASON_VALUE;

typedef enum _MAJOR_ERROR_CODE_VALUE {
	BMC_AUTH_FAIL = 0x1,
	PCH_AUTH_FAIL,
	BMC_BOOT_FAIL,
	ME_BOOT_FAIL,
	ACM_BOOT_FAIL,
	BIOS_BOOT_FAIL,
	PCH_UPDATE_FAIL,
	BMC_UPDATE_FAIL,
	CPLD_UPDATE_FAIL
} MAJOR_ERROR_CODE_VALUE;

typedef enum _MINOR_ERROR_CODE_VALUE {
	ACTIVE_AUTH_FAIL                = 0x1,
	RECOVERY_AUTH_FAIL,
	ACTIVE_RECOVERY_AUTH_FAIL,
	ACTIVE_RECOVERY_STAGING_AUTH_FAIL,
	BMC_WDT_TIMEOUT                 = 0x1,
	BMC_WDT_THREE_STRIKE_TIMEOUT,
	ME_SPS_FW_SUTH_FAIL             = 0x1,
	ME_WDT_TIMEOUT,
	ME_WDT_THREE_STRIKE_TIMEOUT,
	ACM_WDT_TIMEOUT                 = 0x1,
	ACM_WDT_THREE_STRIKE_TIMEOUT,
	IBB_WDT_TIMEOUT                 = 0x1,
	OBB_WDT_TIMEOUT,
	IBB_WDT_THREE_STRIKE_TIMEOUT,
	OBB_WDT_THREE_STRIKE_TIMEOUT,
	PCH_BMC_INVALID_UPD_INTENT      = 0x1,
	PCH_BMC_FW_INVALID_SVN,
	PCH_BMC_FW_UPD_CAPSULE_AUTH_FAIL,
	FW_UPD_EXCEED_MAX_FAIL_ATTEMPT,
	INVALID_UPD_INTENT              = 0x1,
	CPLD_INVALID_SVN,
	CPLD_UPD_CAPSULE_AUTH_FAIL,
	CPLD_UPD_EXCEED_MAX_FAIL_ATTEMPT,
	UPD_NOT_ALLOWED,
	FW_UPD_CAPSULE_AUTH_FAIL
} MINOR_ERROR_CODE_VALUE;

typedef enum _UFM_PROVISONING_STATUS_VALUE {
	COMMAND_BUSY                    = 0X1,
	COMMAND_DONE                    = 0X2,
	COMMAND_ERROR                   = 0X4,
	UFM_LOCKED                      = 0X10,
	UFM_PROVISIONED                 = 0X20,
	PIT_LEVEL_1_ENFORCED            = 0X40,
	PIT_L2_COMPLETE_SUCCESSFUL      = 0X80
} UFM_PROVISONING_STATUS_VALUE;

typedef enum _UFM_PROVISIONING_COMMAND_VALUE {
	ERASE_CURRENT           = 0,
	PROVISION_ROOT_KEY,
	PROVISION_PIT_KEY,
	PROVISION_PCH_OFFSET    = 0X5,
	PROVISION_BMC_OFFSET,
	LOCK_UFM,
	READ_ROOT_KEY,
	READ_PIT_PASSWORD,
	READ_PIT_PCH_SPI_HASH,
	READ_PIT_BMC_SPI_HASH,
	READ_PCH_OFFSET,
	READ_BMC_OFFSET,
	RECONFIG_CPLD,
	ENABLE_PIT_LEVEL_1_PROTECTION = 0X10,
	ENABLE_PIT_LEVEL_2_PROTECTION
} UFM_PROVISIONING_COMMAND_VALUE;

typedef enum _UFM_COMMAND_TRIGGER_VALUE {
	EXECUTE_UFM_COMMAND     = 0X1,
	FLUSH_WRITE_FIFO        = 0X2,
	FLUSH_READ_FIFO         = 0X4
} UFM_COMMAND_TRIGGER_VALUE;

typedef enum _BMC_CHECKPOINTS_VALUE {
	STARTED_EXECUTION_BLOCK = 1,
	NEXT_EXECUTION_BLOCK_AUTH_PASS,
	NEXT_EXECUTION_BLOCK_AUTH_FAIL,
	EXIT_PLATFORM_MANUFACTURER_AUTHORITY,
	STARTED_EXTERNAL_EXECUTION_BLOCK,
	RETURNED_FROM_EXTERNAL_EXECUTION_BLOCK,
	PAUSEING_EXECUTION_BLOCK,
	RESUMING_EXECUTION_BLOCK,
	COMPLETING_EXECUTION_BLOCK,
	ENTERED_MANAGEMENT_MODE,
	lEAVING_MANAGEMENT_MODE,
	HOST_READY_TO_BOOT = 0X80,
	HOST_EXIT_BOOT_SERVICES,
	RESET_HOST,
	RESET_ME,
	RESET_BMC
} BMC_CHECKPOINTS_VALUE;

typedef enum _ACM_BIOS_CHECKPOINT_VALUE {
	EXECUTION_BLOCK_STARTED = 1,
	AUTHENTICATION_FAILED   = 3,
	EXECUTION_BLOCK_PAUSED  = 7,
	EXECUTION_BLOCK_RESUMED,
	EXECUTION_BLOCK_COMPLETED
} ACM_BIOS_CHECKPOINT_VALUE;

typedef enum _BMC_PCH_UPDATE_INTENT_VALUE {
	PCH_ACTIVE      = 0X1,
	PCH_RECOVERY    = 0X2,
	CPLD_ACTIVE     = 0X4,
	BMC_ACTIVE      = 0X8,
	BMC_RECOVERY    = 0X10,
	CPLD_RECOVERY   = 0X20,
	UPDATE_DYNAMIC  = 0X40,
	UPDATE_AT_RESET = 0X80
} BMC_PCH_UPDATE_INTENT_VALUE;

#endif /* PFR_SMBUS_MAILBOX_COMM_H_ */
